1. Field of the Invention
The invention relates to a method for selecting capacitors, and more particularly about an improved method for a charge redistribution digital-to-analog converter to select capacitors and reduce non-linear phenomenon produced by capacitor mismatch.
2. Description of the Related Art
The data weighted averaging method is typically used to reduce non-linear phenomenon produced by capacitor mismatch in a charge redistribution digital-to-analog converter. FIG. 1 is a schematic diagram illustrating the method for selecting capacitors by the typical data weighted averaging method. There are eight capacitors U0xcx9cU7 in FIG. 1. Then, nine continuous signals are input to the charge redistribution digital-to-analog converter. The contexts of the signals are 2, 3, 4, 2, 4, 5, 7, 6, 8 in order. The context of the first input signal is 2. Two capacitors are selected from the capacitors U0xcx9cU7. For the first input signal, the selected capacitors 102 include the capacitors U0 and U1. Then, the context of the second input signal is 3. Three capacitors are selected from the capacitors U0xcx9cU7. Because the last capacitor of the selected capacitors 102 is the capacitor U1, the capacitor U2 and the following two capacitors are selected for the second input signal. The selected capacitors 104 include the capacitors U2, U3 and U4. Next, the context of the third input signal is 4. Four capacitors are selected from the capacitors U0xcx9cU7. Because the last capacitor of the selected capacitors 104 is the capacitor U4, the capacitor U5 and the following three capacitors are selected for the third signal. The selected capacitors 106 include the capacitors U5, U6, U7 and U0. According to the above method, for the fourth input signal, the selected capacitors 108 include the capacitors U1 and U2. For the fifth input signal, the selected capacitors 110 include the capacitors U3xcx9cU6. For the sixth input signal, the selected capacitors 112 include the capacitors U7 and U0xcx9cU3. For the seventh input signal, the selected capacitors 114 include the capacitors U4xcx9cU7 and U0xcx9cU3. For the eighth input signal, the selected capacitors 116 include the capacitors U4xcx9cU7 and U0. For the ninth input signal, the selected capacitors 118 include the capacitors U1xcx9cU7 and U0.
According to the method shown in FIG. 1 to select capacitors, the non-linear phenomenon produced by capacitor mismatch can be reduced. As applied in the charge redistribution digital-to-analog converter, however, some constant input (such as input the signals whose content are 2, 2, 2, 2 or 4, 4 circle) may result in a mismatch error produced by periodic capacitors to reduce electrical characteristics. Thus, the typical data weighted averaging method is improved to reduce the mismatch error produced by periodic capacitors.
FIG. 2 is a schematic diagram illustrating the method for selecting capacitors by the improved data weighted averaging method. For the improved data weighted averaging method, one more capacitor is added to select. As shown in FIG. 2, there are nine capacitors U0xcx9cU8. Then, nine continuous signals are input to the charge redistribution digital-to-analog converter. The contexts of the signals are 2, 3, 4, 2, 4, 5, 7, 6, 8 in order. The context of the first input signal is 2. Two capacitors are selected from the capacitors. For the first input signal, the selected capacitors 202 include the capacitors U0 and U1. Then, the context of the second input signal is 3. Three capacitors are selected from the capacitors U0xcx9cU7. Because the last capacitor of the selected capacitors 202 is the capacitor U1, the capacitor U2 and the following two capacitors are selected for the second input signal. The selected capacitors 204 include the capacitors U2, U3, and U4. Next, the context of the third input signal is 4. Four capacitors are selected from the capacitors U0xcx9cU7. Because the last capacitor of the selected capacitors 204 is the capacitor U4, the capacitor U5 and the following three capacitors are selected for the third input signal. The selected capacitors 206 include the capacitors U5, U6, U7 and U8. According to the above method, for the fourth input signal, the selected capacitors 208 include the capacitors U0 and U1. For the fifth input signal, the selected capacitors 210 include the capacitors U2xcx9cU5. For the sixth input signal, the selected capacitors 212 include the capacitors U6xcx9cU8, U0 and U1. For the seventh input signal, the selected capacitors 214 include the capacitors U2xcx9cU8. For the eighth input signal, the selected capacitors 216 include the capacitors U0xcx9cU5. For the ninth input signal, the selected capacitors 218 include the capacitors U6xcx9cU8 and U0xcx9cU4.
According to the method shown in FIG. 2 to select capacitors, the mismatch error produced by periodic capacitors can be reduced. But applied in the charge redistribution digital-to-analog converter, some constant input (such as input the signals whose content are 1, 1, 1, 1 circle) may result in a non-linear phenomenon. Furthermore, when input and selected capacitors form a regular relationship, the mismatch error produced by periodic capacitors may occur.
The present invention is directed to a method for selecting capacitors in a charge redistribution digital-to-analog converter implemented to reduce the mismatch error produced by periodic capacitors and the non-linear phenomenon produced by capacitor mismatch.
Accordingly, the present invention provides a method for selecting capacitors in a charge redistribution digital-to-analog converter. In the charge redistribution digital-to-analog converter, m capacitors are arranged. The m capacitors comprise an initial capacitor, an address of which is an initial address, and a blank capacitor, an address of which is a blank address. First, a signal is input to the charge redistribution digital-to-analog converter to identify n output units of the charge redistribution digital-to-analog converter. Then, the initial capacitor at the initial address and the following nxe2x88x922 capacitors at the following nxe2x88x922 addresses are continuously selected and if the following nxe2x88x922 capacitors comprise the blank capacitor, the next capacitor is selected instead of the blank capacitor and a new blank capacitor is identified. Next, the initial address is changed to the address of the capacitor next to the last selected capacitor. Finally, the nxe2x88x921 selected capacitors are output for the output units of the charge redistribution digital-to-analog converter. The n and m are positive integers and m greater than n greater than =1.
Accordingly, the present invention also provides a method for selecting capacitors in a charge redistribution digital-to-analog converter. The charge redistribution digital-to-analog converter comprises m capacitors arranged in the charge redistribution digital-to-analog converter, an initial pointer directional to an initial capacitor of m capacitors, and a blank pointer directional to a blank capacitor of the m capacitors. First, a signal is input to the charge redistribution digital-to-analog converter to identify n output units of the charge redistribution digital-to-analog converter. Next, the initial capacitor directed by the initial pointer and the following nxe2x88x922 capacitors are continuously selected and if the following nxe2x88x922 capacitors comprise the blank capacitor directed by the blank pointer, the next capacitor is selected instead of the blank capacitor and the blank pointer is updated. Then, the initial pointer directional is changed to a new initial capacitor next to the last selected capacitor. Finally, the nxe2x88x921 selected capacitors are output for the output units of the charge redistribution digital-to-analog converter. The n and m are positive integers and m greater than n greater than =1.